uCsim, Copyright (C)  Daniel Drotos.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
Type of microcontroller: F380 CMOS cmos
Controller has 15 hardware element(s).
   on cpu[0]
   on simif[0]
  off vcd[0]
   on timer0[0]
   on timer1[1]
   on uart[0]
   on dreg[0]
   on dport[0]
   on port[0]
   on port[1]
   on port[2]
   on port[3]
   on irq[0]
   on timer2[2]
   on port[4]
     R0 R1 R2 R3 R4 R5 R6 R7
     08 70 d4 b2 8a 29 54 48
@R0 9a .  ACC= 0x00   0 .  B= 0x00
@R1 84 .  PSW= 0x00 CY=0 AC=0 OV=0 P=0
SP 0x07 -> 48 54 29 8a b2 d4 70 08
   DPTR= 0x0000 @DPTR= 0x95 149 .
0x0000  ? ff       MOV    R7,A[0K
Memory chips:
  0x000000-0x0000ff      256 variable_storage (32,%08x,0x%02lx)
  0x000000-0x00ffff    65536 rom_chip (8,%02x,0x%04lx)
  0x000000-0x0000ff      256 iram_chip (8,%02x,0x%02lx)
  0x000000-0x00ffff    65536 xram_chip (8,%02x,0x%04lx)
  0x000000-0x00007f      128 sfr_0_chip (8,%02x,0x%02lx)
  0x000000-0x00007f      128 sfr_f_chip (8,%02x,0x%02lx)
Address spaces:
  0x000000-0x0000ff      256 variables (32,%08x,0x%02lx)
  0x000000-0x00ffff    65536 rom (8,%02x,0x%04lx)
  0x000000-0x0000ff      256 iram (8,%02x,0x%02lx)
  0x000080-0x0000ff      128 sfr (8,%02x,0x%02lx)
  0x000000-0x00ffff    65536 xram (8,%02x,0x%04lx)
  0x000000-0x000007        8 regs (8,%02x,0x%01lx)
  0x000000-0x0000ff      256 bits (1,%01x,0x%02lx)
  0x000000-0x000001        2 dptr (8,%02x,0x%01lx)
Address decoders:
  variables 0x00 0xff -> variable_storage 0x00 activated
  rom 0x0000 0xffff -> rom_chip 0x0000 activated
  iram 0x00 0xff -> iram_chip 0x00 activated
  sfr 0x80 0x90 -> sfr_0_chip 0x00 activated
  sfr 0x91 0x95 -> banked
    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
    banks:
      *  0. sfr_0_chip 0x11
         1. -
         2. -
         3. -
         4. -
         5. -
         6. -
         7. -
         8. -
         9. -
        10. -
        11. -
        12. -
        13. -
        14. -
        15. sfr_f_chip 0x11
  sfr 0x96 0xb8 -> sfr_0_chip 0x16 activated
  sfr 0xb9 0xb9 -> banked
    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
    banks:
      *  0. sfr_0_chip 0x39
         1. -
         2. -
         3. -
         4. -
         5. -
         6. -
         7. -
         8. -
         9. -
        10. -
        11. -
        12. -
        13. -
        14. -
        15. sfr_f_chip 0x39
  sfr 0xba 0xbb -> sfr_0_chip 0x3a activated
  sfr 0xbc 0xbc -> banked
    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
    banks:
      *  0. sfr_0_chip 0x3c
         1. -
         2. -
         3. -
         4. -
         5. -
         6. -
         7. -
         8. -
         9. -
        10. -
        11. -
        12. -
        13. -
        14. -
        15. sfr_f_chip 0x3c
  sfr 0xbd 0xbf -> sfr_0_chip 0x3d activated
  sfr 0xc0 0xc2 -> banked
    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
    banks:
      *  0. sfr_0_chip 0x40
         1. -
         2. -
         3. -
         4. -
         5. -
         6. -
         7. -
         8. -
         9. -
        10. -
        11. -
        12. -
        13. -
        14. -
        15. sfr_f_chip 0x40
  sfr 0xc3 0xc7 -> sfr_0_chip 0x43 activated
  sfr 0xc8 0xc8 -> banked
    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
    banks:
      *  0. sfr_0_chip 0x48
         1. -
         2. -
         3. -
         4. -
         5. -
         6. -
         7. -
         8. -
         9. -
        10. -
        11. -
        12. -
        13. -
        14. -
        15. sfr_f_chip 0x48
  sfr 0xc9 0xc9 -> sfr_0_chip 0x49 activated
  sfr 0xca 0xcf -> banked
    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
    banks:
      *  0. sfr_0_chip 0x4a
         1. -
         2. -
         3. -
         4. -
         5. -
         6. -
         7. -
         8. -
         9. -
        10. -
        11. -
        12. -
        13. -
        14. -
        15. sfr_f_chip 0x4a
  sfr 0xd0 0xe3 -> sfr_0_chip 0x50 activated
  sfr 0xe4 0xe4 -> banked
    bank selector: sfr[0xbf] mask=0xf banks=16 act=0
    banks:
      *  0. sfr_0_chip 0x64
         1. -
         2. -
         3. -
         4. -
         5. -
         6. -
         7. -
         8. -
         9. -
        10. -
        11. -
        12. -
        13. -
        14. -
        15. sfr_f_chip 0x64
  sfr 0xe5 0xff -> sfr_0_chip 0x65 activated
  xram 0x0000 0xffff -> xram_chip 0x0000 activated
  regs 0x0 0x7 -> banked
    bank selector: sfr[0xd0] mask=0x18 banks=4 act=0
    banks:
      *  0. iram_chip 0x00
         1. iram_chip 0x08
         2. iram_chip 0x10
         3. iram_chip 0x18
  bits 0x00 0x7f -> bander(8/1) iram_chip 0x20 activated
  bits 0x80 0xff -> bander(8/8) sfr_0_chip 0x00 activated
  dptr 0x0 0x1 -> sfr_0_chip 0x02 activated
